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Complete activation scheme for FPGA-oriented IP cores design protection.

Brice ColombierUgo MuredduMarek LabanOto PeturaLilian BossuetViktor Fischer
Published in: FPL (2017)
Keyphrases
  • hardware design
  • real time
  • case study
  • low cost
  • verilog hdl
  • single chip
  • information processing
  • hardware implementation
  • hardware architecture
  • mobile ipv
  • protection scheme