Low Power Sorters Using Clock Gating.

Preethi K. G. Mohan K. Sudeendra Kumar K. K. Mahapatra

Published in: iSES (2021)

Keyphrases

low power
power reduction
power consumption
power dissipation
low cost
high speed
single chip
power saving
vlsi architecture
digital signal processing
logic circuits
energy efficiency
power management
vlsi circuits
pattern recognition