Reconfigurable Shuffle Network Design in LDPC Decoders.
Jun TangTejas M. BhattVishwas SundaramurthyPublished in: ASAP (2006)
Keyphrases
- network design
- decoding algorithm
- ldpc codes
- power reduction
- low density parity check
- communication networks
- heuristic solution
- low cost
- network design problem
- network architecture
- facility location
- hardware implementation
- noise model
- channel coding
- power consumption
- reverse logistics
- error correction
- interconnection networks
- non binary
- lower bound
- low power
- object oriented