Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell.
Chinnaiyan SenthilpariAjay Kumar SinghKrishna M. DiwakarPublished in: Microelectron. J. (2008)
Keyphrases
- low power
- low power consumption
- logic circuits
- power dissipation
- power consumption
- low cost
- single chip
- high speed
- vlsi architecture
- gate array
- nm technology
- digital signal processing
- signal processor
- design process
- real time
- cmos technology
- ultra low power
- mixed signal
- power reduction
- image sensor
- wireless transmission
- high power
- analog to digital converter
- application specific