Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing.
Ning ZhuWang Ling GohWeija ZhangKiat Seng YeoZhi-Hui KongPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
- low power
- digital signal processing
- high speed
- logic circuits
- power dissipation
- power consumption
- single chip
- low cost
- error tolerant
- low power consumption
- vlsi architecture
- gate array
- cmos technology
- real time
- mixed signal
- data flow
- signal processing
- power reduction
- computer vision
- nm technology
- ultra low power
- embedded systems
- motion estimation
- data structure
- database systems
- data mining