Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.
Chi-Wei WangNicholas P. CarterRichard B. KujothJeffrey J. CookDerek B. GottliebPublished in: FPL (2005)
Keyphrases
- low cost
- single chip
- parallel processing
- general purpose processors
- general purpose
- fine grain
- systolic array
- digital signal
- hardware implementation
- high speed
- distributed memory
- reconfigurable architecture
- field programmable gate array
- memory management
- computation intensive
- database
- computer architecture
- instruction set
- multiprocessor systems
- data flow
- low power
- neural network