A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform.
Praveen Kumar KasettyAniruddha KanhePublished in: Microprocess. Microsystems (2024)
Keyphrases
- pipeline architecture
- hardware implementation
- efficient implementation
- signal processing
- multiscale decomposition
- hardware design
- software implementation
- fpga implementation
- field programmable gate array
- image processing algorithms
- dedicated hardware
- parallel architecture
- hardware architecture
- memory management
- neural network
- real time
- pattern recognition
- feature selection