High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors.
Ram KrishnamurthyPublished in: ARC (2010)
Keyphrases
- energy efficient
- multi core architecture
- wireless sensor networks
- energy consumption
- low overhead
- sensor networks
- single chip
- parallel processing
- low cost
- instruction set
- graphics processing units
- data dissemination
- multi core processors
- energy efficiency
- distributed memory
- base station
- routing protocol
- field programmable gate array
- general purpose
- shared memory
- parallel algorithm
- parallel computing
- parallel computers
- high performance computing
- computing systems
- hardware implementation
- low power
- wireless networks
- data management
- data sets