FPGA design and implementation of the Joint Viterbi Detector Decoder.
Brahim HamadicharefKheong Sann ChanPublished in: ICSPCS (2016)
Keyphrases
- fpga implementation
- hardware design
- efficient implementation
- case study
- hardware architecture
- fpga technology
- hardware implementation
- implementation issues
- design process
- hardware architectures
- design methodology
- field programmable gate array
- single chip
- reconfigurable hardware
- fpga device
- viterbi algorithm
- detection algorithm
- hardware description language
- computational complexity