Power Dissipation Driven FPGA Place and Route Under Delay Constraints.

Kaushik Roy Sharat Prasad

Published in: FPL (1994)

Keyphrases

power dissipation
power reduction
power consumption
low power
digital signal processing
low cost
network on chip
high speed
end to end delay
cmos technology
chip design
finite state machines
power saving
design methodology
hardware implementation
signal processing
real time