A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC.
Gaurav KhuranaAshraf A. KassimTien Ping ChuaMichael B. MiPublished in: IEEE Trans. Consumer Electron. (2006)
Keyphrases
- deblocking filter
- hardware implementation
- parallel architecture
- low bit rate
- low power
- video communication
- blocking artifacts
- signal processing
- efficient implementation
- spatial domain
- video streaming
- power consumption
- data flow
- post processing
- image compression
- motion compensation
- transform domain
- low cost
- discrete cosine transform
- delay insensitive
- image quality
- high frequency
- video codec
- video coding standard
- compressed images
- high definition
- high speed
- variable block size
- bit rate
- computer vision