On-the-Fly Model Checking Under Fairness That Exploits Symmetry.
Viktor GyurisA. Prasad SistlaPublished in: CAV (1997)
Keyphrases
- model checking
- temporal logic
- finite state
- formal verification
- formal specification
- temporal properties
- automated verification
- partial order reduction
- model checker
- process algebra
- timed automata
- symbolic model checking
- epistemic logic
- verification method
- pspace complete
- reachability analysis
- finite state machines
- bounded model checking
- formal methods
- concurrent systems
- linear temporal logic
- computation tree logic
- modal logic
- transition systems
- asynchronous circuits
- symmetry breaking