Low-power dynamic termination scheme using NMOS diode clamping.

Dong-Ho Shin Young-Min Lee Kyu-Hyoun Kim Kwyro Lee

Published in: IEEE J. Solid State Circuits (1999)

Keyphrases

low power
power consumption
low cost
high speed
high power
single chip
logic circuits
vlsi circuits
gate array
power dissipation
low power consumption
digital signal processing
cmos technology
real time
vlsi architecture
power reduction
model checking
computer simulation
signal processor
wireless sensor networks