Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC.
Tung-Chien ChenYu-Han ChenSung-Fang TsaiLiang-Gee ChenPublished in: ICASSP (3) (2006)
Keyphrases
- low power
- motion estimation
- video coding
- deblocking filter
- inter frame
- coding efficiency
- variable block size
- video compression standard
- low complexity
- rate distortion
- macroblock
- low cost
- power consumption
- high speed
- motion vectors
- motion compensated
- video compression
- motion compensation
- single chip
- video codec
- video sequences
- video coding standard
- image sequences
- computational complexity
- rate control
- optical flow
- compression efficiency
- reference frame
- compressed domain
- vlsi architecture
- super resolution
- block matching
- low power consumption
- computer vision
- mode decision
- video quality
- frame rate
- spatial domain
- bit rate
- scalable video coding
- digital signal processing
- bitstream
- vlsi circuits
- image sensor
- error propagation
- intra prediction
- video streams
- power reduction
- real time
- logic circuits
- gate array