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Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264.

Yu-Wen HuangTu-Chih WangBing-Yu HsiehLiang-Gee Chen
Published in: ISCAS (2) (2003)
Keyphrases
  • hardware architecture
  • mpeg avc
  • video coding standard
  • rate distortion
  • video codec
  • hardware implementation
  • coding efficiency
  • image processing
  • video sequences
  • image data
  • visual quality