Login / Signup
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264.
Yu-Wen Huang
Tu-Chih Wang
Bing-Yu Hsieh
Liang-Gee Chen
Published in:
ISCAS (2) (2003)
Keyphrases
</>
hardware architecture
mpeg avc
video coding standard
rate distortion
video codec
hardware implementation
coding efficiency
image processing
video sequences
image data
visual quality