Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Wagner PennyGuilherme CorrêaLuciano AgostiniDaniel PalominoMarcelo Schiavon PortoGabriel L. NazarBruno ZattPublished in: ISCAS (2020)
Keyphrases
- low power
- hardware architecture
- motion estimation
- processing elements
- video compression
- power consumption
- high speed
- low cost
- associative memory
- low complexity
- hardware implementation
- motion compensated
- video coding
- video sequences
- motion compensation
- motion vectors
- optical flow
- power dissipation
- image sequences
- video codec
- block matching motion estimation
- coding efficiency
- rate distortion
- reference frame
- low power consumption
- logic circuits
- field programmable gate array
- block matching
- image sensor
- digital signal processing
- cmos technology
- random access
- inter frame
- nm technology
- video coding standard
- computational complexity
- spatial domain
- general purpose
- mixed signal