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Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification.
Peng Zou
Zhifeng Lin
Xiao Shi
Yingjie Wu
Jianli Chen
Jun Yu
Yao-Wen Chang
Published in:
DAC (2020)
Keyphrases
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model checking
asynchronous circuits
high speed
verification method
bounded model checking
low cost
epistemic logic
real time
routing problem
classical logic
computing systems
formal verification
field programmable gate array
routing algorithm
modal logic
ad hoc networks
wireless sensor networks