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Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU.

Minh Thien TrieuHuong Thien HoangPhong The VoHung Bao VoYoichi Yuyama
Published in: ASICON (2011)
Keyphrases
  • power consumption
  • clock gating
  • low power
  • power reduction
  • energy efficiency
  • power saving
  • power management
  • floating point
  • power dissipation
  • energy saving
  • massively parallel
  • floating point unit