FPGA design of a truncated SVD based receiver for the detection of SEFDM signals.

Ryan C. Grammenos Safa Isam Izzat Darwazeh

Published in: PIMRC (2011)

Keyphrases

automatic detection
design process
case study
verilog hdl
hardware architecture
signal processing
detection algorithm
efficient implementation
embedded systems
hardware implementation
hardware design
neural network
singular value decomposition
low cost
low signal to noise ratio
signal detection
digital signal