Low-power comparator in 65-nm CMOS with reduced delay time.
Mohammad TohidiJens Kargaard MadsenMartijn J. R. HeckFarshad MoradiPublished in: ICECS (2016)
Keyphrases
- low power
- cmos technology
- power consumption
- low cost
- nm technology
- high speed
- single chip
- low voltage
- wireless transmission
- power reduction
- vlsi circuits
- silicon on insulator
- ultra low power
- high power
- vlsi architecture
- image sensor
- logic circuits
- delay insensitive
- digital signal processing
- low power consumption
- power management
- power dissipation
- mixed signal
- power saving
- parallel processing
- signal processor
- gate array