An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding.
Arash ArdakaniMojtaba MahdaviMahdi ShabanyPublished in: ISCAS (2013)
Keyphrases
- turbo codes
- vlsi architecture
- channel coding
- low complexity
- distributed video coding
- error correction
- vlsi implementation
- low power
- real time
- error propagation
- wireless channels
- compressed images
- mode decision
- coding scheme
- computational complexity
- rate allocation
- bit plane
- communication systems
- power consumption
- computer simulation
- high speed
- packet loss
- video compression
- bit rate