A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications.
I-Ning KuZhiwei XuYen-Cheng KuanYen-Hsiang WangMau-Chung Frank ChangPublished in: IEEE J. Solid State Circuits (2012)
Keyphrases
- low power
- analog to digital converter
- power consumption
- wireless communication
- wireless transmission
- mixed signal
- image sensor
- single chip
- wireless networks
- communication networks
- low cost
- short range
- vlsi circuits
- wireless sensor networks
- high speed
- computer simulation
- mobile communication
- vlsi architecture
- low power consumption
- nm technology
- cmos technology
- digital signal processing
- cmos image sensor
- ultra low power
- wireless channels
- power reduction
- power dissipation
- cognitive radio
- wifi
- power supply