, 35-μW, 8.87-ps-resolution CMOS time-to-digital converter using dual-slope architecture.
Yeo Myung KimDoohyun ShonTae Wook KimPublished in: Int. J. Circuit Theory Appl. (2017)
Keyphrases
- analog to digital converter
- cmos image sensor
- mixed signal
- low power
- digital straight line
- circuit design
- data conversion
- high resolution
- low voltage
- image sensor
- high speed
- management system
- analog vlsi
- low cost
- parallel processing
- single chip
- low resolution
- vlsi circuits
- neural network
- multi channel
- network architecture
- design methodology
- design considerations
- software architecture
- high voltage