A Compiler-Controlled Instruction Cache Architecture for an Embedded Low Power Microprocessor.
Xiaoping ZhuTeng-Tiow TayPublished in: CIT (2005)
Keyphrases
- low power
- instruction set
- high speed
- low cost
- embedded systems
- level parallelism
- memory hierarchy
- vlsi architecture
- memory subsystem
- power consumption
- instruction set architecture
- cmos technology
- single chip
- memory access
- nm technology
- silicon on insulator
- design methodology
- low power consumption
- computer architecture
- real time
- application specific
- logic circuits
- high power
- digital signal processing
- floating point
- mixed signal
- signal processor
- vlsi circuits
- multithreading
- main memory
- gate array
- parallel computing
- multi channel
- hardware and software
- general purpose