A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications.

Jermy C. Smith Fred J. Taylor

Published in: IEEE Trans. Computers (1995)

Keyphrases

fault tolerant
systolic array
parallel architecture
fault tolerance
reconfigurable architecture
data flow
distributed systems
load balancing
parallel processing
state machine
hardware implementation
safety critical
real time
high availability
shared memory
concurrency control
parallel implementation