A scalable single-chip multi-processor architecture with on-chip RTOS kernel.
Bart D. TheelenA. C. VerschuerenV. V. Reyes SuárezM. P. J. StevensAntonio NúñezPublished in: J. Syst. Archit. (2003)
Keyphrases
- multi processor
- single chip
- network on chip
- low power
- program execution
- single processor
- low cost
- cmos image sensor
- shared memory
- multi core processors
- signal processor
- distributed memory
- image sensor
- high speed
- parallel architectures
- parallel algorithm
- parallel processors
- color filter array
- parallel programming
- parallel machines
- power consumption