Low Power Design of Precomputation-Based Content-Addressable Memory.

Shanq-Jang Ruan Chi-Yu Wu Jui-Yuan Hsieh

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2008)

Keyphrases

low power
low power consumption
high speed
single chip
low cost
power consumption
vlsi architecture
logic circuits
digital signal processing
gate array
vlsi circuits
power dissipation
high power
cmos technology
design process
mixed signal
power reduction
ultra low power