Implementation of Systolic Co-processor for Deep Neural Network Inference based on SoC.
Erwin SetiawanTrio AdionoPublished in: ISOCC (2018)
Keyphrases
- neural network
- efficient implementation
- inference process
- probabilistic inference
- bayesian networks
- cell broadband engine architecture
- systolic array
- network architecture
- neural network model
- high speed
- pattern recognition
- parallel processing
- prediction model
- bp neural network
- self organizing maps
- multi layer
- graphical models
- multi layer perceptron
- computer architecture
- parallel architecture
- instruction set
- neural network is trained
- expert systems