Power efficient architecture for (3, 6)-regular low-density parity-check code decoder.

Yijun Li Mahmoud Elassal Magdy A. Bayoumi

Published in: ISCAS (4) (2004)

Keyphrases

low density parity check
ldpc codes
error correction
decoding algorithm
distributed video coding
channel coding
low complexity
vlsi architecture
computer simulation
message passing