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Design of 0.35-ps RMS Jitter 4.4-5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology.
Yusong Qiu
Lei Zhao
Feng Zhang
Published in:
Circuits Syst. Signal Process. (2018)
Keyphrases
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cmos technology
power consumption
clock gating
clock frequency
power dissipation
low power
parallel processing
spl times
power reduction
high speed
design methodology
digital signal processing
low frequency
image processing
efficient implementation
user interface
video sequences
multimedia