Formal Verification of Peephole Optimizations in Asynchronous Circuits.
Xiaohua KongRadu NegulescuPublished in: FORTE (2001)
Keyphrases
- asynchronous circuits
- formal verification
- model checking
- temporal logic
- automated verification
- model checker
- process algebra
- bounded model checking
- symbolic model checking
- formal specification
- delay insensitive
- concurrent systems
- program slicing
- artificial intelligence
- quality of service
- optimization strategies
- planning domains
- model based diagnosis
- orders of magnitude