1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology.

Fuding Ge Malay Trivedi Brent Thomas William Jiang Hongjiang Song

Published in: SoCC (2008)

Keyphrases

power consumption
high speed
cmos technology
low power
spl times
low voltage
neural network
power management