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Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving.

Michail ManiatakosMaria K. MichaelYiorgos Makris
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
  • design methodology
  • global optimization
  • protection scheme
  • information systems
  • constrained optimization
  • random access memory
  • high speed
  • information security
  • error correction
  • circuit design
  • memory subsystem