Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC.
Anush BekalShabi TabassumManish GoswamiPublished in: J. Circuits Syst. Comput. (2017)
Keyphrases
- low power
- single chip
- analog to digital converter
- power consumption
- low cost
- vlsi architecture
- low power consumption
- logic circuits
- digital signal processing
- mixed signal
- high speed
- power dissipation
- design process
- gate array
- cmos technology
- ultra low power
- wireless transmission
- high power
- delay insensitive
- cmos image sensor
- real time
- image sensor
- embedded systems
- vlsi circuits
- nm technology
- synthetic aperture radar