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Cache Friendly Parallelization of Neural Encoder-Decoder Models Without Padding on Multi-core Architecture.
Yuchen Qiao
Kazuma Hashimoto
Akiko Eriguchi
Haixia Wang
Dongsheng Wang
Yoshimasa Tsuruoka
Kenjiro Taura
Published in:
IPDPS Workshops (2017)
Keyphrases
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low complexity
multi core architecture
real time
noisy channel