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Cache Friendly Parallelization of Neural Encoder-Decoder Models Without Padding on Multi-core Architecture.

Yuchen QiaoKazuma HashimotoAkiko EriguchiHaixia WangDongsheng WangYoshimasa TsuruokaKenjiro Taura
Published in: IPDPS Workshops (2017)
Keyphrases
  • low complexity
  • multi core architecture
  • real time
  • noisy channel