An area-efficient low-power SCM topology for high performance network-on Chip (NoC) architecture using an optimized routing design.
R. PoovendranS. SumathiPublished in: Concurr. Comput. Pract. Exp. (2019)
Keyphrases
- network on chip
- power dissipation
- low power
- cmos technology
- power consumption
- routing algorithm
- packet switched
- low power consumption
- single chip
- vlsi architecture
- low cost
- high speed
- digital signal processing
- nm technology
- logic circuits
- signal processor
- interconnection networks
- multi processor
- network simulator
- mixed signal
- real time
- design methodology
- routing protocol
- wireless sensor networks
- image sensor
- fault tolerant
- multistage
- multipath
- signal processing
- data management
- image processing