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A 2.0 GHz 4 Mb pseudo-SRAM with on-chip BIST for refresh in 0.18u CMOS technology with LVDS output data bus drivers.

Mehdi BathaeeZed MostoufiHamid GhezelayaghAnahita Afkham
Published in: ICECS (2002)
Keyphrases
  • high speed
  • computer systems
  • data processing
  • low power
  • cmos technology
  • low cost
  • digital images
  • power consumption