10 Gbps implementation of TLS/SSL accelerator on FPGA.
Takashi IsobeSatoshi TsutsumiKoichiro SetoKenji AoshimaKazutoshi KariyaPublished in: IWQoS (2010)
Keyphrases
- xilinx virtex
- field programmable gate array
- hardware implementation
- low cost
- hardware architecture
- parallel implementation
- fpga technology
- fpga implementation
- efficient implementation
- semi supervised learning
- information systems
- high speed
- software implementation
- hardware architectures
- parameter estimation
- parallel architecture
- dedicated hardware
- neural network
- real time