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Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions.
Victor M. Goncalves Martins
Joao Gabriel Reis
Horácio C. Neto
Eduardo Augusto Bezerra
Published in:
FCCM (2015)
Keyphrases
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high speed
hardware implementation
field programmable gate array
hardware architecture
fpga implementation
real time
learning algorithm
dedicated hardware
data sets
information systems
low cost
efficient implementation
real time image processing
pipelined architecture