Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters.
Niccoló NicodemoGaurav NaithaniKonstantinos DrossosTuomas VirtanenRoberto SalettiPublished in: EUSIPCO (2020)
Keyphrases
- memory requirements
- neural network
- field programmable gate array
- memory space
- computational complexity
- pattern recognition
- hardware implementation
- memory usage
- embedded systems
- computing systems
- image processing algorithms
- programmable logic
- parallel computing
- high end
- computational speed
- hardware and software
- computing resources
- general purpose
- object oriented
- case study
- hardware design
- parallel architectures
- hardware architecture
- software implementation
- image processing