Model Checking Controllers with Predicate Inputs.

M. Santhosh Prabhu Pallab Dasgupta

Published in: VLSI Design (2013)

Keyphrases

model checking
temporal logic
model checker
finite state
partial order reduction
temporal properties
verification method
automated verification

control system
computation tree logic
formal verification
symbolic model checking
bounded model checking
reachability analysis
formal specification
formal methods

finite state machines
timed automata
transition systems
pspace complete
first order logic
reinforcement learning
asynchronous circuits
epistemic logic

process algebra
linear temporal logic
concurrent systems
knowledge base
planning domains
satisfiability problem
abstract interpretation