Hardware Acceleration of Parallel Lagged-Fibonacci Pseudo Random Number Generation.
Yu BiGregory D. PetersonG. Lee WarrenRobert J. HarrisonPublished in: ERSA (2006)
Keyphrases
- pseudo random number
- parallel hardware
- random numbers
- massively parallel
- computer architecture
- low cost
- parallel architectures
- parallel execution
- parallel computation
- high end
- real time
- distributed memory
- processing elements
- hardware implementation
- hardware and software
- multi core processors
- parallel architecture
- graphics processing units
- processing units
- parallel computing
- parallel processing
- computer systems
- uniformly distributed
- machine learning
- parallel programming
- parallel processors
- parallel implementation
- computing systems
- naive bayes