Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.
Tomasz MadajczakHenryk KrawczykPublished in: PARELEC (2006)
Keyphrases
- shared memory
- massively parallel
- parallel architectures
- low cost
- hardware and software
- real time
- commodity hardware
- parallel algorithm
- hardware implementation
- image processing
- data sets
- message passing
- computing systems
- high end
- address space
- parallel processing
- scheduling algorithm
- response time
- computational power
- information systems
- computing power
- hardware design
- genetic algorithm