A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 μV DC offset.
Vincent QuiquempoixPhilippe DevalAlexandre BarretoGabriele BelliniJerry CollingsJános MárkusJosé B. SilvaGabor C. TemesPublished in: ESSCIRC (2005)
Keyphrases
- low power
- power consumption
- low cost
- single chip
- high speed
- analog to digital converter
- compression algorithm
- low power consumption
- logic circuits
- high power
- wireless transmission
- vlsi architecture
- vlsi circuits
- digital signal processing
- incremental algorithms
- cmos technology
- mixed signal
- image sensor
- power reduction
- power dissipation
- signal processor
- nm technology
- ultra low power