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10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Ahmed Elkholy
Ahmed Elmallah
Mohamed Elzeftawi
Ken Chang
Pavan Kumar Hanumolu
Published in:
ISSCC (2016)
Keyphrases
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power consumption
clock gating
high speed
nm technology
low power
cmos technology
clock frequency
power reduction
hd video
power supply
power dissipation
floating point
low cost
real time
packet loss
hardware implementation
artificial neural networks