A floating point multiplier performing IEEE rounding and addition in parallel.

Woo-Chan Park Tack-Don Han Shin-Dug Kim Sung-Bong Yang

Published in: J. Syst. Archit. (1999)

Keyphrases

floating point
floating point arithmetic
fixed point
square root
instruction set
sparse matrices
fast fourier transform
graphics processing units
higher order
low cost
approximation algorithms
interval arithmetic
memory bandwidth