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Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers.

Giuseppe CaireJavier Ventura-TravesetM. HollreiserEzio Biglieri
Published in: J. VLSI Signal Process. (1995)
Keyphrases
  • vlsi implementation
  • high speed
  • vlsi architecture
  • low power
  • filter bank
  • real time
  • image coding
  • associative memory
  • coding scheme
  • subband
  • fir filters
  • pattern recognition
  • artificial neural networks
  • bitstream