Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA.
Uli KretzschmarArmando AstarloaJesús LázaroMikel GarayJavier Del SerPublished in: ReConFig (2012)
Keyphrases
- real time
- power consumption
- power reduction
- high speed
- hardware implementation
- video sequences
- computational efficiency
- temporal information
- temporal reasoning
- data transmission
- verilog hdl
- gate array
- digital signal processors
- real time image processing
- high robustness
- field programmable gate array
- data acquisition
- image processing