Architecture for video coding on a processor with an ARM and DSP cores.
Yung-Sung HuangBin-Chang ChieuPublished in: Multim. Tools Appl. (2011)
Keyphrases
- video coding
- bit rate
- video compression
- motion compensated
- motion estimation
- rate distortion
- multi core processors
- motion compensation
- level parallelism
- video quality
- high speed
- motion vectors
- rate control
- video codec
- high definition
- image and video compression
- motion estimation and compensation
- parallel architecture
- instruction set
- macroblock
- signal processing
- motion compensated prediction
- central processing unit
- compression efficiency
- real time
- block based motion estimation
- video coder
- visual quality
- bitstream
- scalable video coding
- advanced video coding
- video decoder
- processor core
- wyner ziv video coding
- digital signal processor
- temporal redundancy
- error resilience
- error criterion
- video encoder
- prediction error
- video sequences
- multi layer
- multimedia
- packet loss
- coding efficiency
- block matching motion estimation
- image processing
- object based coding
- computer vision