Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design.
M. RullánCarles FerrerJoan OliverDiego MateoAntonio RubioPublished in: ED&TC (1996)
Keyphrases
- circuit design
- cmos technology
- detailed design
- efficient implementation
- high speed
- power dissipation
- image analysis
- statistical analysis
- power consumption
- case study
- implementation issues
- delay insensitive
- architectural design
- design considerations
- low power
- design process
- low voltage
- future development
- correlation analysis
- quantitative analysis
- parallel processing
- feature space